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2383BS–WLAN–01/04 Features •Wireless Interface Following the IEEE 802.11b Standard •Two Ethernet MAC Units (EMU) Interfaces with 10/100 Mbits Ethernet Physical Layer Transceivers through Standard MII Ports •Dual ARM7TDMI ® RISC Processor Architecture •Inter-networking ARM7TDMI (INWARM) with 16 Kbytes Program and Data Cache Controls the Ethernet MAC Units and Provides the Bridging Functions between Ethernet and Wireless Interfaces •WLAN ARM7TDMI (WLANARM) with a Dedicated 32 Kbytes Program Memory Coordinates the 802.11b MAC Functionality •802.11b MAC Unit with 512-byte Transmit and 128-byte Receive FIFOs •SDRAM Interface Supporting up to 256 MBytes of External Memory Shared between Both Processors •32-bit DMA Channels Are Used for Data Packet Transfers between the SDRAM and the MAC Units •Enciphering/Deciphering of Wireless Data On-the-fly Ensures Maximum Privacy of Data •SPI Interface and Eight GPIO Pins that Can Be Used As Slave-Select Pins •A Bootstrap ROM Is Used in the Initialization Phase by the WLAN ARM ® to Execute a Code Downloading Procedure from an SPI Flash to Its Internal Program Memory •UART with 16-byte Receive and Transmit FIFO and Programmable Baud Rate up to 921 Kbaud •Supports 802.1f (IAPP) and Tap-Dance ™ (Atmel proprietary roaming protocol) •2.5 V for Core and 3.3 V for I/O •Different Packages, Depending on the Requirements Block Diagram Inter-networking ARM Core (INWARM) Decoder/Arbiter/ Bridge #2 Timers, Interrupt Controller #2 Cache Memory External Memory Interface Internal Memory #1 Common Memory Interface Controller WLAN ARM Core (WLANARM) Decoder/Arbiter/ Bridge #1 Timers, Interrupt Controller #1 Ethernet Processor 0 MAC Support Unit (MSU) Ethernet Processor 1 UART SPI Dual Ethernet to IEEE 802.11b WLAN Bridge- on-a-Chip (DEW-B) AT76C511 Summary Note: This is a summary document. A complete document is available under NDA. For more information, please con- tact your local Atmel sales office.