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Revision 2.3 April. 2002 1 A4 A3 A2 A1 A0 CE DQ0 DQ1 DQ2 DQ3 VCC GND DQ4 DQ5 DQ6 DQ7 WE A17 A16 A15 A14 A13 A5 A6 A7 OE UB LB DQ15 DQ14 DQ13 DQ12 GND VCC DQ11 DQ10 DQ9 DQ8 NC A8 A9 A10 A11 A12 1 2 3 4 8 10 11 12 14 16 18 20 22 43 41 39 37 35 34 33 31 29 27 25 23 BS616LV4010EC BS616LV4010EI 5 6 7 9 13 15 17 19 21 44 42 40 38 36 32 30 28 26 24 R0201-BS616LV4010 POWER DISSIPATION SPEED ( ns ) STANDBY ( ICCSB1, Max ) Operating ( ICC, Max ) PRODUCT FAMILY OPERATING TEMPERATURE Vcc RANGE Vcc=3.0VVcc=3.0VVcc=3.0V PKG TYPE BS616LV4010DCDICE BS616LV4010EC BS616LV4010AC TSOP2-44 BGA-48-0608 BS616LV4010BC +0 O C to +70 O C2.7V ~ 3.6V70 / 1008uA20mA BGA-48-0810 BS616LV4010DIDICE BS616LV4010EI BS616LV4010AI TSOP2-44 BGA-48-0608 BS616LV4010BI -40 O C to +85 O C2.7V ~ 3.6V70 / 10012uA25mA BGA-48-0810 Very Low Power/Voltage CMOS SRAM 256K X 16 bit • Very low operation voltage : 2.7 ~ 3.6V • Very low power consumption : Vcc = 3.0V C-grade: 20mA (Max.) operating current I -grade: 25mA (Max.) operating current 0.5uA (Typ.) CMOS standby current • High speed access time : -70 70ns (Max.) at Vcc = 3.0V -10 100ns (Max.) at Vcc = 3.0V •Automatic power down when chip is deselected • Three state outputs and TTL compatible • Fully static operation • Data retention supply voltage as low as 1.5V • Easy expansion with CE and OE options • I/O Configuration x8/x16 selectable by LB and UB pin The BS616LV4010 is a high performance, very low power CMOS Static Random Access Memory organized as 262,144 words by 16 bits and operates from a wide range of 2.7V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.5uA and maximum access time of 70/100ns in 3V operation. Easy memory expansion is provided by an active LOW chip enable(CE) and active LOW output enable(OE) and three-state output drivers. The BS616LV4010 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616LV4010 is available in DICE form, JEDEC standard 44-pin TSOP Type II package and 48-pin BGA package. DESCRIPTION FEATURES Row Decoder Memory Array 2048 x 2048 Column I/O Write Driver Sense Amp Column Decoder Data Buffer Output A9 A8 A7 Data Input Buffer Control Gnd Vcc OE DQ0 A15 A1 16 16 16 16 WE CE DQ15 A0 A13 A14 A2 14 128 2048 BLOCK DIAGRAM 2048 22 A17 A16 A10 A12 A6 A11 A3 Address Input Buffer A5 Address Input Buffer . . . . UB . . . . LB PRODUCT FAMILY PIN CONFIGURATIONS Brilliance Semiconductor Inc.reserves the right to modify document contents without notice. BS616LV4010 A4 BSI