BS616LV8021 datasheet pdf

Revision 2.3 April 2002 1 BSI Very Low Power/Voltage CMOS SRAM 512K x 16 or 1M x 8 bit switchable BS616LV8021 R0201-BS616LV8021 POWER DISSIPATION SPEED (ns) STANDBY (I, Max)CCSB1 Operating (I, Max)CC PRODUCT FAMILY OPERATING TEMPERATURE Vcc RANGE Vcc=3.0VVcc=3.0VVcc=3.0V PKG TYPE BS616LV8021AC+0 O C to +70 O C2.7 BS616LV8021AI-40 O C to +85 O C2.7 V ~ 3.6V70 / 10016uA20mABGA-48-0608 V ~ 3.6V70 / 10024uA25mABGA-48-0608 „BLOCK DIAGRAM The BS616LV8021 is a high performance, very low power CMOS Static Random Access Memory organized as 524,288 words by 16 bits or 1,048,576 bytes by 8 bits selectable by CIO pin and operates from a wide range of 2.7V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 1uA and maximum access time of 70/100ns in 3.0V operation. Easy memory expansion is provided by an active HIGH chip enable2(CE2), active LOW chip enable1(CE1), active LOW output enable(OE) and three-state output drivers. The BS616LV8021 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616LV8021 is available in 48-pin BGA type. • Very low operation voltage : 2.7 ~ 3.6V • Very low power consumption : Vcc = 3.0V C-grade: 20mA (Max.) operating current I-grade : 25mA (Max.) operating current 1uA (Typ.) CMOS standby current • High speed access time : -70 70ns (Max.) at Vcc=3.0V -10 100ns (Max.) at Vcc=3.0V •Automatic power down when chip is deselected • Three state outputs and TTL compatible • Fully static operation • Data retention supply voltage as low as 1.5V • Easy expansion with CE1, CE2 and OE options • I/O Configuration x8/x16 selectable by CIO, LB and UB pin „DESCRIPTION „FEATURES Brilliance Semiconductor Inc. reserves the right to modify document contents without notice. Row Decoder Memory Array 2048 x 4096 Column I/O Write Driver Sense Amp Column Decoder Data Buffer Output A1 A2 A3 Data Buffer Input Control Vss Vdd OE WE CE1 D15 D0 A11 A7 A17 A8 A12 A13 16(8) 16(8) 16(8) 16(8) 16(18) 256(512) 4096 2048 22 A10 A9 A0 A6 A4 A16 A14 Address Input Buffer A5 Address Input Buffer . . . . UB . . . . LB A15 CIO CE2 (SAE) A18 LBOEA0A1A2 CE2 D9 D10 VSS D3 VC C D12 D14 D1 3 A1 4A 1 5 12A 13 WE D7 A18 A8A9 D8UBA3A4CE1D0 A5A6D1D2 D11A17A7 VCC A16D4VSS D5D6 D15CIO.A A10A11SAE. A B C D E F G H 123456 VSS „PRODUCT FAMILY „PIN CONFIGURATIONS 48-Ball CSP top View

Features

• • Very low operation voltage : 2.7 ~ 3.6V
• • Very low power consumption :
• • High speed access time :
• -70 70ns (Max.) at Vcc=3.0V
• -10 100ns (Max.) at Vcc=3.0V
• •Automatic power down when chip is deselected
• • Three state outputs and TTL compatible
• • Fully static operation
• • Data retention supply voltage as low as 1.5V
• • Easy expansion with CE1, CE2 and OE options
• • I/O Configuration x8/x16 selectable by CIO, LB and UB pin