BS616LV8025 datasheet pdf

Revision 2.4 April 2002 1 BSI Very Low Power/Voltage CMOS SRAM 512K x 16 or 1M x 8 bit switchable BS616LV8025 R0201-BS616LV8025 The BS616LV8025 is a high performance, very low power CMOS Static Random Access Memory organized as 524,288 words by 16 bits or 1,048,576 bytes by 8 bits selectable by CIO pin and operates from a wide range of 4.5V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 3uA and maximum access time of 55/70ns in 5.0V operation. Easy memory expansion is provided by an active HIGH chip enable2(CE2), active LOW chip enable1(CE1), active LOW output enable(OE) and three-state output drivers. The BS616LV8025 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616LV8025 is available in 48-pin BGA type. POWER DISSIPATION SPEED (ns) STANDBY (I CCSB1 , Max) Operating (I CC , Max) PRODUCT FAMILY PKG TYPE BS616LV8025BC+0 O C to +70 O C 4.5V ~ 5.5V55/7030uA45mABGA-48-0810 BS616LV8025BI-40 O C to +85 O C 4.5V ~5.5V55/70 100uA 50mABGA-48-0810 • Very low operation voltage : 4.5 ~ 5.5V • Very low power consumption : Vcc = 5.0V C-grade: 45mA (Max.) operating current I-grade : 50mA (Max.) operating current 3uA (Typ.) CMOS standby current • High speed access time : -55 55ns (Max.) at Vcc= 5.0V -70 70ns (Max.) at Vcc= 5.0V • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Fully static operation • Data retention supply voltage as low as 1.5V • Easy expansion with CE1, CE2 and OE options • I/O Configuration x8/x16 selectable by CIO, LB and UB pin „DESCRIPTION „FEATURES „BLOCK DIAGRAM „PRODUCT FAMILY Brilliance Semiconductor Inc. reserves the right to modify document contents without notice. Row Decoder Memory Array 2048 x 4096 Column I/O Write Driver Sense Amp Column Decoder Data Buffer Output A1 A2 A3 Data Buffer Input Control GND Vdd OE WE CE1 D15 D0 A11 A7 A17 A8 A12 A13 16(8) 16(8) 16(8) 16(8) 16(18) 256(512) 4096 2048 22 A10 A9 A0 A6 A4 A16 A14 Address Input Buffer A5 Address Input Buffer . . . . UB . . . . LB A15 CIO CE2 (SAE) A18 „PIN CONFIGURATIONS LB A2 CE2 D8 UB A3A4 CE1 D0 VSS D3 VCC VCC D12 A15 D15CIO. A12A13 WE D7 A18 A8A9 OEA0A1 D9D10A5A6D1D2 D11A17A7 A16D4VSS D14D13A14 D5D6 A10A11SAE. A B C D E F G H 123456 VSS 48-Ball CSP top View OPERATING TEMPERATURE Vcc RANGE Vcc=5VVcc=5VVcc=5V

Features

• • Very low operation voltage : 4.5 ~ 5.5V
• • Very low power consumption :
• • High speed access time :
• -55 55ns (Max.) at Vcc= 5.0V
• -70 70ns (Max.) at Vcc= 5.0V
• • Automatic power down when chip is deselected
• • Three state outputs and TTL compatible
• • Fully static operation
• • Data retention supply voltage as low as 1.5V
• • Easy expansion with CE1, CE2 and OE options
• • I/O Configuration x8/x16 selectable by CIO, LB and UB pin