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Revision 2.4 April 2002 1 BSI Ultra Low Power/Voltage CMOS SRAM 512K x 16 or 1M x 8 bit switchable The BS616UV8020 is a high performance, ultra low power CMOS Static Random Access Memory organized as 524,288 words by 16 bits or 1,048,576 bytes by 8 bits selectable by CIO pin and operates from a wide range of 1.8V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.4uA and maximum access time of 70/100ns in 2V operation. Easy memory expansion is provided by an active HIGH chip enable2(CE2), and active LOW chip enable1(CE1), an active LOW output enable(OE) and three-state output drivers. The BS616UV8020 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS616UV8020 is available in 48-pin BGA type. POWER DISSIPATION SPEED (ns) STANDBY (ICCSB1, Max) Operating (ICC, Max) PRODUCT FAMILY OPERATING TEMPERATURE Vcc RANGE Vcc=2 VVcc=2VVcc=3VVcc=2VVcc=3V PKG TYPE BS616UV8020BC+0 O C to +70 O C1.8V ~ 3.6V70 / 1002uA3uA15mA20mABGA-48-0810 BS616UV8020BI-40 O C to +85 O C1.8V ~ 3.6V70 / 1004uA6uA20mA25mABGA-48-0810 • Ultra low operation voltage : 1.8 ~3.6V • Ultra low power consumption : Vcc = 2.0V C-grade: 15mA (Max.) operating current I-grade : 20mA (Max.) operating current 0.4uA (Typ.) CMOS standby current Vcc = 3.0V C-grade: 20mA (Max.) operating current I-grade : 25mA (Max.) operating current 0.5uA (Typ.) CMOS standby current • High speed access time : -70 70ns (Max.) at Vcc=2V -10 100ns (Max.) at Vcc=2V • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Fully static operation • Data retention supply voltage as low as 1.5V • Easy expansion with CE1, CE2 and OE options • I/O Configuration x8/x16 selectable by CIO, LB and UB pin DESCRIPTION FEATURES BLOCK DIAGRAM PRODUCT FAMILY Brilliance Semiconductor Inc. reserves the right to modify document contents without notice. BS616UV8020 Row Decoder Memory Array 2048 x 4096 Column I/O Write Driver Sense Amp Column Decoder Data Buffer Output A1 A2 A3 Data Buffer Input Control Vss Vdd OE WE CE1 D15 D0 A11 A7 A17 A8 A12 A13 16(8) 16(8) 16(8) 16(8) 16(18) 256(512) 4096 2048 22 A10 A9 A0 A6 A4 A16 A14 Address Input Buffer A5 Address Input Buffer . . . . UB . . . . LB A15 CIO CE2 (SAE) A18 PIN CONFIGURATIONS R0201-BS616UV8020 LBOEA0A1A2 CE2 D8UBA3A4CE1D0 D9D10A5A6D1D2 VSS D3 VC C VCC D12A16D4 VSS A15 D15 CIO.A12A13 WE D7 D11A17A7 D14D13A14 D5D6 A18 A8A9 A10A11 SAE. A B C D E F G H 123456 VSS 48-Ball CSP top View