HYMP112P72CP8-C4-1.PDF datasheet pdf

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.7 / Jun. 2009 1 240pin Registered DDR2 SDRAM DIMMs based on 1Gb version C This Hynix Registered Dual In-Line Memory Module (DIMM) series consists of 1Gb version C DDR2 SDRAMs in Fine Ball Grid Array (FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb version C based Registered DDR2 DIMM series provide a high performance 8 byte interface in 5.25" width form factor of industry standard. It is suitable for easy interchange and addition. FEATURES ORDERING INFORMATION Part NameDensityOrganization # of DRAMs # of ranks Parity Support HYMP112P72CP8-C4/Y5/S6/S51GB128Mx7291O HYMP125P72CP8-C4/Y5/S6/S52GB256Mx72182O HYMP125P72CP4-C4/Y5/S6/S52GB256Mx72181O HYMP151P72CP8-C4/Y5/S6/S54GB512Mx72364O HYMP151P72CP4-C4/Y5/S6/S54GB512Mx72362O HYMP31GP72CMP4-C4/Y58GB512Mx72724O HYMP112R72CP8-E3/C41GB128Mx7291X HYMP125R72CP4-E3/C42GB256Mx72181X HYMP151R72CP4-E3/C44GB512Mx72362X •JEDEC standard Double Data Rate2 Synchro- nous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply •All inputs and outputs are compatible with SSTL_1.8 interface •8 Bank architecture •Posted CAS •Programmable CAS Latency 3, 4, 5, 6 •OCD (Off-Chip Driver Impedance Adjustment) •ODT (On-Die Termination) •Fully differential clock operations (CK & CK) •Programmable Burst Length 4 / 8 with both sequential and interleave mode •Auto refresh and self refresh supported •8192 refresh cycles / 64ms •Serial presence detect with EEPROM •DDR2 SDRAM Package: 60 ball(x4/x8) •133.35 x 30.00 mm form factor •RoHS compliant

Features

• •JEDEC standard Double Data Rate2 Synchro-
• 0.1V Power Supply
• •All inputs and outputs are compatible with
• •8 Bank architecture
• •Posted CAS
• •Programmable CAS Latency 3, 4, 5, 6
• •OCD (Off-Chip Driver Impedance Adjustment)
• •ODT (On-Die Termination)
• •Fully differential clock operations (CK & CK)
• •Programmable Burst Length 4 / 8 with both
• •Auto refresh and self refresh supported
• •8192 refresh cycles / 64ms
• •Serial presence detect with EEPROM
• •DDR2 SDRAM Package: 60 ball(x4/x8)
• •133.35 x 30.00 mm form factor
• •RoHS compliant